The present invention relates to an image processor system having a function for performing image processing using the content of a plurality of image memories.
The typical image processor system, as shown in FIG. 1, has an image processor 11, a plurality of image memories 12-1 through 12-3, and a CPU 13 for controlling the image processor 11 and image memories 12-1 through 12-3. The CPU 13 and the image processor 11 are connected through an internal bus 14, and the respective image memories 12-1 through 12-3 are connected to each other through a memory bus 15. A memory control unit 16 (to be referred to as an MCU hereinafter) is connected to the buses 14 and 15.
The image processor system as described above can combine a plurality of images. The processor 11 receives image data from, for example, the memories 12-1 and 12-2 and ORes the received data. The image combining procedures are as follows:
(i) The CPU 13 reads out data from the image memory 12-1 through the MCU 16 and transfers the readout data to the image processor 11.
(ii) The CPU 13 reads out data from the image memory 12-2 through the MCU 16 and transfers the readout data to the processor 11.
(iii) The image processor 11 ORes the image data read out from the memories 12-1 and 12-2.
(iv) The ORed result is written in the memory 12-3 under the control of the CPU 13.
(v) The operations of items (i) through (iv) above are repeated for a required screen region (window), and synthetic image data is obtained in the memory 12-3.
However, when data is read out from a plurality of image memories and image processing is performed in the conventional image processor system described above, data must be read out serially. In addition, the CPU 13 is involved in each data read operation from the memories. For this reason, the conventional image processor system requires a long processing time and the effeciency of CPU processing is degraded.